The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6700149 B1

Expired

Date of Patent:

Mar. 02, 2004

Filed:

Apr. 01, 2002

Circuit configuration for forming a mos capacitor with a lower voltage dependence and a lower area requirement

Applicant:

Inventors:

Thomas Tille, München, TW;

Doris Schmitt-Landsiedel, Ottobrunn, DE;

Jens Sauerbrey, München, DE;

Assignee:

Infineon Technologies AG, Munich, DE;

Attorney:

Primary Examiner:

George Eckert

Int. Cl.

CPC ...

H01L 2/7088 ;

U.S. Cl.

CPC ...

H01L 2/7088 ;

Abstract

A circuit configuration for providing a capacitance includes short-channel MOS transistors that are reverse-connected in series or in parallel, and that have the same channel type. When the short-channel MOS transistors are operated exclusively in the depletion mode in the required voltage range, the useful capacitance is increased, because of intrinsic capacitances, as compared with circuit configurations having conventional long-channel MOS transistors. These circuits greatly reduce the area taken up and reduce the costs.

Find Patent Forward Citations

Tille, Thomas. (2004). Circuit configuration for forming a mos capacitor with a lower voltage dependence and a lower area requirement (U.S. Patent No. 6700149). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6700149

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile