The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2004
Filed:
Dec. 14, 2001
Adi Srinivasan, Fremont, CA (US);
David L. Allen, Fremont, CA (US);
Sequence Design, Inc., Santa Clara, CA (US);
Abstract
A clock tree insertion method for distributing a clock signal in an integrated circuit design includes providing a physical design representative of the integrated circuit design, specifying a location for a root node of the clock tree in the physical design, constructing an array of buffers as the clock tree where the array of buffers is constructed to minimize the maximum insertion delay from the root node to the clock signal endpoints and to meet a predefined maximum insertion delay constraint, identifying locations in the clock tree where clock skew violations occur and correcting the clock skew violations by introducing delay at buffer locations in the clock tree having the fastest clock signal arrival times, and identifying locations in the clock tree where minimum insertion delay violations occur and correcting the minimum insertion delay violations by slowing down the arrival times of clock signal endpoints of the clock tree.