The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2004

Filed:

Apr. 28, 2000
Applicant:
Inventors:

Kazushige Ayukawa, Kokubunji, JP;

Jun Sato, Mitaka, JP;

Takashi Miyamoto, Tokyo, JP;

Kenichiro Omura, Higashimurayama, JP;

Hiroyuki Hamasaki, Higashimurayama, JP;

Hiroshi Takeda, Higashiyamato, JP;

Makoto Takano, Sayama, JP;

Isamu Mochizuki, Tachikawa, JP;

Yasuhiko Hoshi, Iruma, JP;

Kazuhiro Hirade, Kokubunji, JP;

Ryuichi Murashima, Kokubunji, JP;

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/00 ;
U.S. Cl.
CPC ...
G06F 1/00 ;
Abstract

A semiconductor device is connected to a CPU, a memory and I/O devices to serve as a data transfer bridge for efficient data transfer between the memory and the I/O devices. A CPU interface and a plurality of I/O interfaces included in a bridge chip are connected through an internal bus to a memory interface included in the bridge chip. Each I/O interface has a read/write buffer and a DMAC. An arbiter included in the bridge chip determines a bus master for which data transfer is permitted in response to requests for data transfer from each of the CPU interface and the DMAC to the memory. Each of the I/O interfaces has a control function to skip part of areas in the memory when transferring data between the memory and the I/O interface.


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