The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2004
Filed:
Jan. 11, 2001
Bryan Coin, Campbell, CA (US);
Michael J. Ransford, Millersville, MD (US);
David A. Schwarten, Ellicott City, MD (US);
Chao Jiang, Ellicott City, MD (US);
Iqbal M. Dar, Marriottsville, MD (US);
Andrei Csipkes, Alpharetta, GA (US);
Ciena Corporation, Linthicum, MD (US);
Abstract
A method and apparatus for performing parallel asynchronous testing of a plurality of optical modules utilizes state machines that may be implemented in a common controller. Desired optical tests are selected by an operator. The invention determines if a testing process or instrument required for the selected optical tests is available. A COM port may also be locked for each of the selected optical tests from among a plurality of COM ports to prevent interference between different tests. By reserving resources such as COM ports and testing instruments in this fashion the invention may asynchronously initiate execution of the selected optical tests. If a resource such as a COM port, testing process or instrument is not currently available, the test is place in COM port and testing queues to await availability of that resource. Once a test is completed, the resource is unlocked so that one of the state machines may asynchronously initiate another test. Various displays are generated so that an operator may view the progress of each of the tests. A database is utilized to store test results as well as test recipes and test instrument drivers that aid in the control of a testing architecture.