The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2004

Filed:

Aug. 17, 2000
Applicant:
Inventors:

Young-Gun Ko, Seoul, KR;

Byung-Sun Kim, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/712 ; H01L 2/900 ;
U.S. Cl.
CPC ...
H01L 2/712 ; H01L 2/900 ;
Abstract

The present invention relates to a highly integrated SOI semiconductor device and a method for fabricating the SOI semiconductor device by reducing a distance between diodes or well resistors without any reduction in insulating characteristics. The device includes a first conductivity type semiconductor substrate and a surface silicon layer formed by inserting an insulating layer on the semiconductor substrate. A trench is formed by etching a predetermined portion of surface silicon layer, insulating layer and substrate to expose a part of the semiconductor substrate to be used for an element separating region, and a STI is formed in the trench. A transistor is constructed on the surface silicon layer surrounded by the insulating layer and STI with a gate electrode being positioned at the center thereof and with source/drain region being formed in the surface silicon layer of both edges of the gate electrode for enabling its bottom part to be in contact with the insulating layer. A first groove is formed between the STI at one side of the transistor by etching the surface silicon layer and insulating layer to expose a predetermined portion of an active region of a second conductivity type well in the semiconductor substrate. A second groove is formed between the STI at one side of the first groove by etching the surface silicon layer and insulating layer to expose a predetermined portion of the active region of the semiconductor substrate. A first diode diffusion region of a first conductivity type is formed in a second conductivity type well under the first groove, and a second diode diffusion region of a second conductivity type is formed in the semiconductor substrate under the second groove.


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