The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2004
Filed:
Dec. 12, 2001
Sergej B. Gashkov, Moscow, RU;
Alexander E. Andreev, San Jose, CA (US);
Aiguo Lu, Cupertino, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A circuit embodied in an integrated circuit is characterized by an architecture having a minimal depth defined by a recursive expansion of output functions h_n=OR(h_k, AND(v_k, h_{n−k})) and v_n=AND(v_k, v{n−k}), where k=F_l and n−k=F_{l−1}, satisfies F_l<n=F_{l+1}, {F_l} is a Fibonacci series and n is the number of bits of an input to the circuit. In one form, the circuit is a comparator having output functions h_n and v_n that depend from input functions U[i]=AND(NOT(A[i]), B[i]) and V[i]=OR(NOT(A[i]), B[i]), where A[i] and B[i] are inputs to the comparator, and functions h_n, v_n defined as h_n=h_n(U[ ], U[ ], V[ ], . . . , U[n−1], V[n−1])=OR(U[n−1], AND(V[n−1], U[n−2]), . . . , AND(V[n−1], . . . , V[ ], U[ ])), and v_n=v_n(V[ ], . . . , V[n− ])=AND(V[ ], . . ., V[n−1]). In one form, the comparator includes an LEQ input that identifies strict or non-strict inequality comparison by the comparator. The depth is further minimized by a distribution of negations of elements forming the circuit. A computer process is described to carry out the design, including mapping 2-input elements from a cell library of 3-input elements.