The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2004
Filed:
Jul. 27, 2001
David Smith, Bristol, GB;
STMicroelectronics Limited, Almondsbury Bristol, GB;
Abstract
Integrated circuitry including a clock circuit powered by a first power supply and a secondary circuit powered by a second power supply. The secondary circuit includes a control signal output for supplying a control signal to the clock circuit and a clock data output for outputting new clock data to the clock circuit. The clock circuit includes: clock generator means for generating current clock data and outputting it to the secondary circuit; detector means for monitoring voltage from the second power supply and generating a system reset signal for supply to the secondary circuit in the event the voltage falls below a predetermined level; a first latch having a reset operable by a predetermined state of the system reset output generated by the detector means; a comparator accepting as inputs the control signal from the secondary circuit and an output of the first latch; and a multiplexor accepting as data inputs the clock data from the secondary circuit and the clock data from the clock circuit, and accepting as a control input the output of the comparator. The integrated circuitry is configured such that when the secondary circuit is not asserted and the control signal is asserted, the current clock data in the clock circuit is replaced with the new clock data. Moreover, when the first latch is reset, the comparator and multiplexor prevent current clock data from being replaced by data from the secondary circuit.