The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2004
Filed:
Jan. 13, 2003
Kingston Technology Corporation, Fountain Valley, CA (US);
Abstract
A vertically integrated chip scale package (CSP) assembly comprising two or more single chip package subassemblies having an upper level CSP subassembly superimposed directly above a lower level CSP subassembly. The lower-most CSP subassembly in the vertical stack contains an array of solder balls for interconnection to a printed wiring board. The vertical electrical connection between the upper and lower level package subassemblies is accomplished by using wire bonding from perimeter wire bonding pads located on an upper level substrate extension to matching perimeter wire bonding pads located on a lower level substrate extension that is longer in length than the upper level substrate extension. The stacked package subassemblies are bonded together by using a thin adhesive material, and the perimeter wire bonds are encapsulated by an encapsulant for protection. The assembled vertical stack has the appearance of a single CSP but is shorter in height than two individual packages that are stacked together with solder ball interconnects located therebetween.