The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 2004
Filed:
Oct. 02, 2000
Andrej A. Zolotykh, Moskovskaya, RU;
Elyar E. Gasanov, Moscow, RU;
Alexander S. Podkolzin, Moscow, RU;
Valery B. Kudryavtsev, Moscow, RU;
LSI Logic Corporation, Milpitas, CA (US);
Abstract
The present invention includes methods for optimizing integrated circuit design by identifying a buffer tree in the integrated circuit design, the buffer tree having a plurality of vertices, each representing one of a buffer and an inverter, and also having branches, between the vertices, each representing an electrical connection. A plurality of optimization devices are applied in a random sequence to the vertices of the buffer tree. Such devices can include, for example, cell type modification; insertion of one buffer; insertion of several buffers; interchange of two grandchildren; making a grandchild into a child; making a child a grandchild; interchanging a child and a grandchild; eliminating two inverters; removing one buffer; removing more than one buffer; and removing two inverters.