The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 2004
Filed:
Jan. 31, 2002
Applicant:
Inventors:
Kochung Lee, Sunnyvale, CA (US);
Ming Qu, San Jose, CA (US);
Xueping Jiang, Cupertino, CA (US);
Xiang Zhu, Sunnyvale, CA (US);
Assignee:
Lattice Semiconductor Corp., Hillsboro, OR (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/920 ;
U.S. Cl.
CPC ...
H03K 1/920 ;
Abstract
High speed CML logic gate systems for providing selected Boolean logic functions. Two halves of a substantially symmetric first system, having a relatively small number ( ) of CMOS transistors, are used to generate any of the logic functions AND, NAND, OR and NOR. Two halves of a substantially symmetric second system having another small number ( ) of transistors are used to generate any of the logic functions XOR, XNOR and NOT. In either system, the sum of currents passing through certain voltage-controlling gates is substantially constant.