Semiconductor device and method of fabricating the same

Abstract

A method of fabricating a semiconductor device which has a cell array with non-volatile memory transistors and a peripheral circuit including a first transistor and a second transistor as driven by a lower voltage than the first transistor is disclosed. The method includes the steps of forming over a semiconductor substrate a first gate dielectric film for use in the first transistor, selectively etching the first gate dielectric film in the cell array region to expose the substrate, forming over the exposed substrate a second gate dielectric film which is for use as a tunnel dielectric film of the memory transistors, forming a first gate electrode material film over the first and second gate dielectric films, selectively etching the first gate electrode material film and its underlying first gate dielectric film in the second transistor region, forming over the exposed substrate a third gate dielectric film which is for use in the second transistor, forming a second gate electrode material film over the third gate dielectric film, and forming gates of the respective transistors while letting the gates at least partly include the first and second gate electrode material films.