The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2004

Filed:

Oct. 16, 2001
Applicant:
Inventors:

Chih-Kung Lee, Taipei, TW;

Long-Sun Huang, Taipei, TW;

Wen-Jong Chen, Taipei, TW;

Ching-Heng Tang, Taipei, TW;

Ching-Hua Lee, Tao Yuan, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/146 ;
U.S. Cl.
CPC ...
H01L 2/146 ;
Abstract

The present invention is a wafer level integrating method for bonding an un-sliced wafer including image sensors and a wafer-sized substrate including optical components thereon. A zeroth order light reflective substrate is provided between the un-sliced wafer and the wafer-sized substrate. The image sensors are either CMOS or CCD image sensors. The wafer-sized substrate is a transparent plate and the optical components thereon include a blazed grating, a two-dimensional microlens array or other optical-functional elements. The wafer-sized substrate is bonded onto the zeroth order light reflective substrate by an appropriate optical adhesive to form a composite substrate. Bonding pads and bumps are provided at corresponding positions on the bonding surface of the un-sliced wafer and the composite substrate respectively so that the composite substrate and the un-sliced wafer can be bonded together through a reflow process. Alternatively, the composite substrate and the un-sliced wafer can be bonded together by cold compression or thermal compression. The resultant wafer is then sliced into separated image sensors for further packaging, such as CLCC, PLCC, QFP, QFN or QFJ. Alternatively, the resultant wafer can be packaged through a wafer-level chip scale packaging process.


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