The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2004
Filed:
Jul. 25, 2002
Applicant:
Inventors:
Assignee:
Other;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 ;
U.S. Cl.
CPC ...
H03L 7/06 ;
Abstract
A DLL circuit or the like is configured so as to be capable of measuring the optimum number of cycles for a delay amount from the input of an external clock to the output of data through the use of a variable delay circuit and performing lock according to the measured number of cycles, whereby a clock generation circuit having a wide lock range can be implemented regardless of the performance of the variable delay circuit and a clock access time.
Okuda, Yuichi. (2004). Clock generation circuit, control method of clock generation circuit, clock reproducing circuit, semiconductor memory device, and dynamic random access memory (U.S. Patent No. 6677791). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6677791
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile