The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2004
Filed:
Jun. 27, 2002
Hong Q. Hou, Albuquerque, NM (US);
Charlie X. Wang, Albuquerque, NM (US);
Wenlin Luo, Albuquerque, NM (US);
Emcore Corporation, Somerset, NJ (US);
Abstract
Apparatus and method for on-wafer burn-in of a semiconductor device. In a preferred embodiment, the present invention is realized using an auto-prober commonly used in scan-testing of semiconductor devices. Specifically, in one embodiment, the auto-prober is programmed to sequentially apply an elevated current to each semiconductor device on a wafer. During the application of the elevated current, which substantially exceeds the normal operating current of the device, performance characteristics of the device, including its output power, is detected and registered. Preferably, each device is subjected to multiple scans by the elevated current. The device's performance characteristics is then analyzed. If a device exhibits consistent power output over different scans, it is not likely to suffer from infant mortality. If the device exhibits a shift in power output over successive scans, the device is likely to run into early failure and should be rejected. The multiple scans by the elevated current also stabilize device performance, avoiding further shift when the device is used in normal operation. Significantly, the present invention utilizes existing testing equipment to implement on-wafer burn-in and does not require an extended burn-in period, thereby providing an easily implemented and cost-effective method and system for on-wafer burn-in not achievable in prior art approaches.