The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2004

Filed:

Oct. 09, 2002
Applicant:
Inventors:

Hsing T. Tuan, Cupertino, CA (US);

Li-Chun Li, Los Gatos, CA (US);

Vei-Han Chan, San Jose, CA (US);

Assignee:

Mosel Vitelic, Inc., Hsin Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/134 ;
U.S. Cl.
CPC ...
G11C 1/134 ;
Abstract

In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.


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