The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2004
Filed:
Jul. 12, 2002
Applicant:
Inventors:
Wai Lo, Lake Oswego, OR (US);
David Chan, San Jose, CA (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/358 ;
U.S. Cl.
CPC ...
H01L 2/358 ;
Abstract
Embodiments of the invention include a calibration standard for semiconductor metrology tools. The standard comprises a substrate having a surface with a calibration layer formed thereon. A protective layer is formed over the underlying calibration layer. The calibration layer and protective layer are each formed to precise tolerances. The invention also includes methods for forming a calibration standard for semiconductor metrology tools.
Lo, Wai. (2004). Thin film cmos calibration standard having protective cover layer (U.S. Patent No. 6674092). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6674092
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile