The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2003
Filed:
Nov. 27, 2001
Anwar Ali, San Jose, CA (US);
Farshad Ghahghahi, Los Gatos, CA (US);
Edwin M. Fulcher, Palo Alto, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
An input/output array of an integrated circuit comprises concentric rings of input/output tiles. The peripheral input/output tiles are adjacently arranged along the periphery of the integrated circuit to form a peripheral ring. Each of the peripheral input/output tiles is associated with a corresponding peripheral input/output device group having x number of input/output devices. Each peripheral input/output tile includes x number of signal contacts for coupling signals to corresponding ones of the x number of input/output devices, y number of input/output driver voltage contacts for coupling a source voltage to drivers of the x number of input/output devices, and z number of ground contacts. The interior input/output tiles are adjacently arranged within the interior of the integrated circuit to form n number of substantially concentric interior rings, where n is greater than or equal to one.