The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2003
Filed:
Oct. 09, 2002
Ching-chang Shih, Tainan, TW;
Chun-an Tu, Tainan, TW;
Tsung-chi Hsu, Changhua, TW;
Wei-feng Lin, Hsinchu, TW;
Ming-huan Lu, Hsinchu, TW;
Abstract
A partially embedded decoupling capacitor is provided as an integral part of a semiconductor chip for reducing delta-I noise. The semiconductor chip includes a plurality of embedded metal layers, a passivation layer formed above the plurality of embedded metal layers as a topmost layer of the semiconductor chip, and a plurality of bonding pads disposed on the passivation layer. A surface planar metal pattern is formed on the passivation layer and electrically connected to one of the plurality of embedded metal layers through one of the plurality of bonding pads or a via hole opened on the passivation layer. For example, the surface planar metal pattern may be connected to a power layer or a ground layer of the semiconductor chip. Therefore, the partially embedded decoupling capacitor is made up of the surface planar metal pattern as an electrode, others of the plurality of embedded metal layers as opposite electrodes, and the passivation layer sandwiched therebetween as a dielectric layer. Since connected to one of the plurality of embedded metal layers, the surface planar metal pattern further serves as a heat sink for dissipating heat directly from the inside of the semiconductor chip.