The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 23, 2003
Filed:
Apr. 09, 2003
Applicant:
Inventors:
David J. Alcoe, Vestal, NY (US);
Eric A. Johnson, Greene, NY (US);
Matthew M. Reiss, Endwell, NY (US);
Charles G. Woychik, Vestal, NY (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/352 ; H01L 2/940 ;
U.S. Cl.
CPC ...
H01L 2/352 ; H01L 2/940 ;
Abstract
A method for providing a package for a semiconductor chip that minimizes stresses and strains that arise from differential thermal expansion on chip-to-substrate or chip-to-card interconnections. A collar element of one or more elements is provided. Adhesive material connects the collar element to the electric device and to the substrate that supports it, forming a unitary electrical package.
Alcoe, David. (2003). Method of forming an apparatus to reduce thermal fatigue stress on flip chip solder connections (U.S. Patent No. 6667557). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6667557
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile