The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2003
Filed:
May. 22, 2002
Alexander E. Andreev, San Jose, CA (US);
Vojislav Vukovic, Santa Clara, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
The present invention is directed to a spanning tree method for K dimensional space. To address timing driven buffer insertion and clock routing problems clusters of points must be constructed in 3-dimensional space. The first and second dimensions are coordinates on a plane, while the third dimension is time which is arrival pin time for buffers insertion and clock latency for clock routing. In a first aspect of the present invention, a method includes partitioning an input set of points into a binary tree of partitions so that each leaf partition has maximally a defined number of points. Graph edges are made for the points by connecting each point to its closest points in every of 2 subspaces and the number of graph nodes is then reduced to a predefined value.