The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2003

Filed:

Nov. 12, 2002
Applicant:
Inventors:

Chaochieh Tsai, Hsih-chu, TW;

Shyhchyi Wong, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01J 2/940 ;
U.S. Cl.
CPC ...
H01J 2/940 ;
Abstract

A method and structure for a device with a signal line over a semiconductor structure where the signal line is formed over the ground plane, passivation layer, and polyimide layer. We provide a semiconductor structure comprising a substrate having devices formed thereover and a plurality of insulating and conductive layers thereover. Next, we form ground plane over the semiconductor structure. The ground plane is the top metal layer over an inter metal dielectric layer. We then form a passivation layer over the ground plane. We form a first dielectric (e.g., polyimide) layer over the passivation layer. Subsequently, we form a signal line over the first dielectric layer. The signal line is formed by a plating or printing. We form a second dielectric layer (e.g., polyimide over the signal line and the first dielectric layer.


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Tsai, Chaochieh. (2003). Lossless microstrip line in cmos process (U.S. Patent No. 6664635). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6664635

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