The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2003

Filed:

May. 20, 2002
Applicant:
Inventors:

Ilya Grodnensky, Foster City, CA (US);

Steve Slonaker, San Mateo, CA (US);

Assignee:

Nikon Precision, Inc., Belmont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/176 ; H01L 2/166 ; H01L 2/358 ; G01B 1/114 ;
U.S. Cl.
CPC ...
H01L 2/176 ; H01L 2/166 ; H01L 2/358 ; G01B 1/114 ;
Abstract

Variation in position of test marks formed of overlapping exposed features imaged by an imaging structure such as that of a lithography tool are characterized at high speed and with extremely high accuracy by imaging test marks formed in resist or on a target or wafer by a lithographic process, collecting irradiance distribution data and fitting a mathematical function to respective portions or regions of output data corresponding to a test mark of a test mark pattern such as respective maxima or minima regions or other regions of the irradiance distribution data to determine actual location and shift of position of respective patterns of test marks. Metrology fields are formed of patterns of test marks on test wafers or production wafers preferably including a critical dimension exposed at different focus distances and/or illumination conditions to capture position/aberration data for the imaging structure. The imaging structure can then be adjusted or corrected to minimize or eliminate aberrations of performance of the imaging structure or the performance on a complete lithographic process and/or to achieve overlay positioning with high accuracy and minimal requirements for wafer space.


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