The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2003
Filed:
Nov. 23, 1999
Joe H. Salmon, Placerville, CA (US);
Andrew Volk, Granite Bay, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A system having several clock domains must have domain clocks properly aligned before powering up from a low-power or power-down mode. The domain clocks can be quickly aligned to enable fast system start-up if the clocks are forced into a rough alignment before a fine alignment process begins. Initially, a phase offset between the domain clocks is determined using a sync pulse, which indicates a location of one of the domain clocks relative to the other domain clock. Next, the domain clocks are forced into a minimum phase offset configuration by phase stalling one of the domain clocks. The phase stalling includes adjusting the pulse width of one of the domain clocks to force the clock into a rough alignment with the other domain clock. Finally, the domain clocks are fine aligned, and the system is placed into a normal power mode.