The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2003

Filed:

Jun. 01, 2000
Applicant:
Inventors:

Boaz Pianka, Kochav Yair, IL;

Biniamin Shatit, Yehuda, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D 3/24 ;
U.S. Cl.
CPC ...
H03D 3/24 ;
Abstract

A synchronized frequency generating system is provided which includes a main crystal clock, for producing a basic frequency F , a channel sampling phase locked loop (PLL) unit, connected to the main crystal clock, for converting the basic frequency F into a channel sampling frequency F , a voice sampling PLL unit, connected to the main crystal clock, for converting the basic frequency F into a voice sampling frequency F , a time tracking unit, connected to the channel sampling PLL unit, for detecting signal characteristics so as to determine a channel sampling frequency phase change value &Dgr;&phgr; and a frame timing phase change value &Dgr;&phgr; , and a phase controller, connected to the voice sampling PLL. The phase controller receives channel sampling frequency phase adjustment data and determines a voice sampling frequency phase change value &Dgr;&phgr; . The phase controller provides the voice sampling frequency phase change value &Dgr;&phgr; to the voice sampling PLL.


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