The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2003

Filed:

Feb. 19, 2002
Applicant:
Inventors:

Sharon L. Moriarty, Mountain View, CA (US);

Zineng Fan, Santa Clara, CA (US);

Dirk D. Brown, Sunnyvale, CA (US);

Che-Yu Li, Ithaca, NY (US);

Assignee:

High Connection Density, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 5/26 ;
U.S. Cl.
CPC ...
G11C 5/26 ;
Abstract

A memory module with any combination of driver line terminators, power supply circuits, and components integral to a memory control subsystem mounted directly on the memory module for use with high speed, impedance-controlled memory buses. The memory module may be formed on a conventional printed circuit card with unpacked or packed memory chips attached directly to the memory module. Including the additional functionality directly on the memory modules improves the EMC/EMI performance as well as signal quality and integrity, thereby enhancing the memory subsystem performance. Such designs may also eliminate the need for bus exit connections, thereby allowing the freed-up connection capacity to be used to address additional memory capacity on the module. Another embodiment features a module with the additional features but without memory devices.


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