All digital built-in self-test circuit for phase-locked loops

Abstract

In general, a built-in self test circuit and method is provided that measures error in any periodic signal and, particularly, a Phase Lock Loop (PLL) output clock signal. The circuit includes a short-pulse generator that generates a short-pulse signal having the same frequency as the phase lock loop output clock signal. Accordingly, a delay chain, including a plurality of delay elements, generates N delayed pulses from the short-pulse signal. A hit-pulse generator receives the N delayed pulses and compares each delayed pulse with the phase lock loop output clock signal 2 times, such that the hit-pulse generator also generates a hit-pulse when both signals are high. It also generates a hit count which represents the number of hit-pulses. After each of the N delayed pulses are compared with the clock signal 2 times, a comparator compares a predetermined set of threshold values corresponding to the cumulative distribution of jitter for a PLL clock signal with the hit count. When the hit count and one of the predetermined set of threshold values are equivalent, the storage unit stores the value of N. A processing unit calculates the error of the PLL clock signal using each stored value of N which directly relates to the cumulative distribution of jitter found in the PLL clock signal.