Integrated circuit with differing gate oxide thickness

Abstract

A semiconductor process for producing two gate oxide thicknesses within an integrated circuit in which a semiconductor substrate having a first region and a second region is provided. The first region and the second region are laterally displaced with respect to one another. A nitrogen species impurity distribution is then introduced into the first region of the semiconductor substrate. Thereafter, a gate dielectric layer is grown on an upper surface of the semiconductor substrate. The gate dielectric has a first thickness over the first region of the semiconductor substrate and a second thickness over the second region of the semiconductor substrate. The first thickness is less than the second thickness. In a CMOS embodiment of the present invention, the first region of the semiconductor substrate comprises p-type silicon while the second substrate region comprises n-type silicon. Preferably, the step of introducing the nitrogen species impurity distribution into the semiconductor substrate is accomplished by thermally oxidizing the first substrate region in a nitrogen bearing ambient. In a presently preferred embodiment, the nitrogen bearing ambient includes N O, NH , O and HCl in an approximate ratio of 60:30:7:3. In alternative embodiments the nitrogen bearing ambient includes NO, O and HCl in an approximate ratio of 90:7:3 or N O, O and HCl in an approximate ratio of 90:7:3. The introduction of the nitrogen species impurity into first substrate region may alternatively be accomplished with rapid thermal anneal processing.