Test signal generating circuit of a semiconductor device with pins receiving signals of multiple voltage levels and method for invoking test modes

Abstract

A signal generating circuit of a semiconductor device comprises n input test pins for receiving respective coded input signals. At least one of the input signals is coded in more than two possible levels, such as 3 levels or four levels. The device also includes an indicator I/O signal generators, each coupled respectively with an associated input test pin. Each indicator signal generator generates two-level indicator signals in response to the coded input signal received by its associated input test pin. A decoder receives the indicator signals to produce decoded signals, and a mode selecting circuit generates mode selecting signals with the decoded signals responsive to mode setting signals. Each indicator signal generators outputs a regular signal when the input test signal is an ordinary low, a control signal when the input test signal is an ordinary high, and a higher first level signal when the input test signal is a super high. If more than three levels are used, the indicator signal generator further generates corresponding signals for these higher values.