The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2003
Filed:
Jul. 18, 2000
Applicant:
Inventors:
Han Quang Nguyen, Allentown, PA (US);
Manosha S. Karunatilaka, Marlborough, MA (US);
Assignee:
Agere Systems Inc., Allentown, PA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/52 ;
U.S. Cl.
CPC ...
G06F 7/52 ;
Abstract
Disclosed is a method and apparatus for accomplishing high speed multiplication of binary numbers using a single clock cycle to achieve the same computational power provided by the multiple clock cycle shift register configurations or the asynchronous multistate logic configurations of the prior art. “Virtual shifts” are achieved by allocating one or more positions, within a register storing the partial products, as place holders, typically zeroes. These place holders can be inserted in a single clock cycle and do not require the multi-staged shift register configurations of the prior art.