The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2003
Filed:
Jun. 27, 2001
Applicant:
Inventors:
Kenneth R. Smits, San Ramon, CA (US);
Bharat Bhushan, Cupertino, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/208 ;
U.S. Cl.
CPC ...
G06F 1/208 ;
Abstract
A cache memory organized into banks of subarrays includes repeaters for connecting to the data provided by the subarrays to a global data bus. The repeaters comprise a logic gate providing either a NAND or NOR function coupled in series with an inverter. The logic gate has a first input connected to receive a first logic value of a bus line, and a second input coupled to receive data output from a subarray. The inverter drives the first logic value onto the bus line when the cache bank subarray is inactive, and drives the data value from the subarray onto the bus line when the cache bank subarray is activate.