The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2003

Filed:

Dec. 21, 2001
Applicant:
Inventor:

David GenLong Chow, Los Altos, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 1/122 ;
U.S. Cl.
CPC ...
G11C 1/122 ;
Abstract

A ferroelectric memory includes wordlines that cross over bitlines with a ferroelectric cell at each crossing. When reading a select cell of the array, sneak currents are drawn from an active bitline. An integration amplifier begins integrating charge propagated by the active bitline, and an active wordline receives a read level voltage. A first integration value is then obtained from the integration amplifier. Following the first integration, the integration amplifier is cleared and the voltage of the active wordline reduced to a quiescent level. Integration and wordline activation are again performed to obtain a second integration value. The second value is subtracted from the first, and the difference compared to a threshold to determine a data value.


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