The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2003
Filed:
Aug. 03, 2001
Naotaka Tanaka, Tokyo, JP;
Hideo Miura, Tokyo, JP;
Yoshiyuki Kado, Tokyo, JP;
Ikuo Yoshida, Tokyo, JP;
Takahiro Naito, Tokyo, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
In order to realize a semiconductor device and a manufacturing method thereof which can keep with a high reliability an electric connection between each of bump pads formed on LSI chips and each of electrode pads formed on an interconnection substrate, within an guaranteed temperature range, a thermal expansion coefficient of an adhesive ( ) is in the range of 20 to 60 ppm, and an elastic modulus of a build-up portion ( ) is in the range of 5 to 10 GPa. Further, the build-up portion ( ) is constituted by a multi-layer build-up substrate in which buid-up portion a peak value (a glass transition temperature) of a loss coefficient exists within a range of 100° C. to 250° C. and does not exist within a range of 0° C. to 100° C. By setting or selecting the physical properties in the manner disclosed above, it is possible to realize a semiconductor device and a manufacturing method thereof which can keep with a high reliability an electric bonding between the bump pads ( ) formed on the LSI chips ( ) and the electrode pads ( ) on the interconnection substrate ( ) within an guaranteed temperature range.