The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2003

Filed:

May. 30, 2002
Applicant:
Inventor:

Li-Chin Tien, Taipei, TW;

Assignee:

Etron Technology, Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 ;
U.S. Cl.
CPC ...
H03L 7/06 ;
Abstract

A particular wide band interface circuit provides an interface between a very fast slope clock signal input and a very slow slope voltage controlled delay cell of a delay lock loop. The invention generates the internal clock signal to track the slope of each delay stage, whether it is a higher frequency for which the slope of the delay stage is faster or a lower frequency for which the slope of the delay stage is slower. The integrated circuit includes a voltage bias portion, an analog clock input portion, circuit devices for interfacing with clock frequency inputs over all the available frequency range, and an output portion for producing clock signals. The invention applies to the multiple delay stages of a delay lock loop.


Find Patent Forward Citations

Tien, Li-Chin. (2003). Interface circuit of various clock period between a fast slope signal and a very slow slope, voltage controlled delay cell (U.S. Patent No. 6642761). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6642761

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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