The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2003
Filed:
Oct. 13, 2000
Akira Mitsui, Yokohama, JP;
Atsushi Hayashi, Tokyo, JP;
Kiyoshi Matsumoto, Yokohama, JP;
Hiromichi Nishimura, Yokohama, JP;
Yasuhiro Sanada, Yokohama, JP;
Makoto Noshiro, Chigasaki, JP;
Kazuo Sunahara, Chigasaki, JP;
Other;
Abstract
The present invention has an object to provide an integrated circuit device having a Cu wiring, using a barrier layer which facilitates planarization. The present invention relates to an integrated circuit device having a Cu wiring layer, a barrier layer therefor and a dielectric layer, wherein the barrier layer is represented by a compositional formula of TaO N (the range of x being 0<x<2.5, and the range of y being 0<y<1). Further, the present invention relates to an integrated circuit device having a Cu wiring layer, a barrier layer therefor and a dielectric layer, wherein the barrier layer is represented by a compositional formula of Ta M O N (M being at least one member selected from the group consisting of elements of Groups 3, 4, 6, 7, 8, 9, 10, 12, 13 and 14 of the long form of the periodic table, the range of a being 0<a<1, the range of b being 0<b<2.5, and the range of c being 0<c<1).