The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2003

Filed:

Dec. 12, 2001
Applicant:
Inventors:

Nobuhiko Sawaki, Nagoya-shi, Aichi, JP;

Yoshio Honda, Mie, JP;

Norikatsu Koide, Tenri, JP;

Katsuki Furukawa, Sakai, JP;

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 3/10336 ; H01L 3/1109 ; H01L 3/112 ; H01L 3/300 ; H01L 3/10312 ;
U.S. Cl.
CPC ...
H01L 3/10336 ; H01L 3/1109 ; H01L 3/112 ; H01L 3/300 ; H01L 3/10312 ;
Abstract

A semiconductor device includes a silicon substrate and a compound semiconductor layer formed on a main plane of the silicon substrate. The compound semiconductor layer is represented by the general formula of In Ga Al N (where x+y+z=1, 0≦x≦1, 0≦y≦1, 0≦z≦1). The silicon substrate includes a trench having as a slope a plane inclined 62 degrees from the main plane of the silicon substrate, or a plane inclined in a range within 3 degrees in an arbitrary direction from the inclined plane. The compound semiconductor layer is formed on the slope. The semiconductor device includes compound semiconductor layers represented by Al Ga In N (where x+y+z=1, 0≦x≦1, 0≦y≦1, 0≦z≦1) on a silicon substrate. The silicon substrate has a main plane constituted by a plane in a range of ±5 degrees in an arbitrary direction from a (112) plane. The compound semiconductor layers are formed on the main plane.


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