Method to reduce lot-to-lot variation of array threshold voltage in a dram device

Abstract

A new method to reduce variation in an output parameter by selection of an optimal process recipe in the manufacture of an integrated circuit device is achieved. The method may be used to reduce the array voltage threshold in a DRAM circuit by compensating the source/drain ion implantation by calculating a predicted array voltage threshold. The integrated circuit device wafer is measured to obtain a present set of process parameter values. A predicted value of an output parameter is calculated by evaluating a first equation at the present set of process parameter values. The first equation is derived from a plurality of previous sets of process parameter values and the corresponding plurality of sets of output parameter values. The difference between the predicted value of the output parameter and a target value of the output parameter is the output parameter delta. A process recipe offset is calculated by evaluating a second equation at the output parameter delta. The second equation is derived from the plurality of selectable process recipes and the plurality of corresponding output parameter values. An optimal process recipe is selected from the plurality of selectable process recipes by adding the process recipe offset to the target process recipe to compensate the output parameter and to thereby reduce the variation.