Cmos integrated circuit devices and substrates having unstrained silicon active layers

Abstract

CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si Ge layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si Ge layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peal Ge concentration level is greater than x&equals;0.15 and the concentration of Ge in the Si Ge layer varies from the peak level to a level less than about x&equals;0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si Ge layer varies from the peak level where 0.2<x<0.4 to a level where x&equals;0 at the first junction. The Si Ge layer also has a retrograded arsenic doping profile therein relative to the surface.