The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2003
Filed:
Jun. 06, 2001
Shuji Sone, Tokyo, JP;
NEC Electronics Corporation, , JP;
Abstract
An interlayer insulating film and a first via connected to a diffusion layer in a MOS transistor are formed on the diffusion layer. Then, a low dielectric constant film for a first layer copper interconnection, and the first layer copper interconnection connected to the first via are formed. Then, an etching stopper film, an interlayer insulating film, and a low dielectric constant film for a second layer copper interconnection are formed in this order. Then, a via hole is formed in the etching stopper film and the interlayer insulating film, and a groove is formed in the low dielectric constant film for the second layer copper interconnection. A barrier metal layer is then formed. Thereafter, Ar ions are implanted. At the time, the implantation energy is 50 keV, and the dose is 1×10 cm . A second via and the second layer copper interconnection are formed, and annealing is performed at a temperature of 400° C.