The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2003
Filed:
Mar. 26, 1999
Rohit Kapur, Cupertino, CA (US);
Thomas W. Williams, Boulder, CO (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
In a computer implemented synthesis system, a method of generating a test pattern for use in testing device with ATE (automated test equipment). The computer implemented steps of receiving a netlist specification representing a design to be realized in physical form and storing the netlist specification in a computer memory unit, and simulating the netlist using the computer implemented synthesis system. Using the simulation instantiated within the synthesis system, deterministic test pattern generation is performed to obtain a first portion (partial) of a test pattern. The test pattern is operable to detect a fault in the circuit netlist once speculative test pattern generation is performed to obtain a remaining portion of the test pattern. The first portion and the remaining portion of the test pattern comprise a test vector operable to detect the fault when used with automated test equipment for testing a device resulting from the design.