The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2003
Filed:
Jun. 24, 2002
Aron T. Lunde, Boise, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
A semiconductor substrate, probe card, and methods for stressing and testing dies on a semiconductor substrate are provided. The semiconductor substrate, typically a semiconductor wafer, comprises dies disposed thereon and a redistribution layer (RDL) for routing signals from a test circuit into dies on the substrate that are not currently under probe. The RDL includes look-ahead contacts associated with a first die set that are electrically connected by traces to dies of a second die set. Upon contact of elements of the probe tester with the look-ahead contacts, required Vcc power, GND ground potential and signals from the probe tester are routed through the traces to the die of the die set not currently under probe. The dies can comprise a built-in self-stress (BISS) circuit and/or a built-in self-test (BIST) circuit for implementing a stress or test sequence. The look-ahead contacts allow for overlapping or substantially simultaneously stressing and/or testing dies of dies of a die set currently under probe and dies of a second die set located prior to or after the current probe head position (i.e., not under probe).