Non-redundant nonvolatile memory and method for sequentially accessing the nonvolatile memory using shift registers to selectively bypass individual word lines

Abstract

A memory including a plurality of memory word lines and a sequential addressing circuit is provided. The sequential addressing circuit comprises at least one sequential shift register including at least one logic gate and at least one word flag cell for each of the word lines. Enablement of each memory word line depends upon the state of the word flag cell. An enable or access bit is shifted sequentially through the sequential. addressing circuit to select each of the word lines. The enable or access bit selectively bypasses or skips a word line depending on the state of its corresponding word flag cell. A method for accessing a nonvolatile writeable memory is also described. The method comprises determining at least one non-operational or defective memory bit cell of a nonvolatile writeable memory. At least one word line of the nonvolatile writeable memory is masked out, wherein the at least one word line is coupled to the at least one non-operational operational memory bit cell. The nonvolatile writeable memory is sequentially addressed in read and write cycles, wherein the at least one word line coupled to the at least one non-operational memory bit cell is bypassed. The sequential shift register may include a plurality of Johnson counter shift registers.