The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2003
Filed:
Apr. 11, 1997
Robert E. Larsen, Shingle Springs, CA (US);
Harry Q. Pon, Sacramento, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A low-power input buffer for a nonvolatile writeable memory is described. The low-power input buffer accepts input signals having one of a number of pairs of logic levels. The low-power input buffer provides output signals having a pair of logic levels that may differ from the logic levels of the input signal. The low-power input buffer comprises an inverter that receives an input signal, a circuit with a relatively low voltage drop, and a feedback pull-up device. The circuit with the relatively low voltage drop causes the low-power input buffer to accept input signals having one pair of logic levels while providing signals that may have a different pair of logic levels. The feedback pull-up device prevents the low-power input buffer from drawing leakage current. The low-power input buffer is coupled to the nonvolatile writeable memory and coupled to the same power supply output as the nonvolatile writeable memory. The low-power input buffer uses input signals having logic levels compatible with complementary metal-oxide semiconductor (CMOS) technology.