Frequency synthesizer including pll with fractional division

Abstract

A digital compensation filtering technique is provided that enables indirect phase locked loop modulation with a digital modulation data stream having a bandwidth that exceeds, perhaps by an order of magnitude, the bandwidth characteristic of the phase locked loop. A modulation data receiver is provided for receiving from a modulation source digital input modulation data having a bandwidth that exceeds the cutoff frequency characteristic of the phase locked loop frequency response. A digital processor is coupled to the modulation data receiver for digitally processing the input modulation data to amplify modulation data at frequencies higher than the phase locked loop cutoff frequency. This digital processor is connected to the phase locked loop frequency divider to modulate the divider based on the digitally-processed input modulation data, whereby a voltage controlled oscillator of the phase locked loop is controlled to produce a modulated output carrier signal having a modulation bandwidth that exceeds the phase locked loop cutoff frequency. The digital processing of the modulation data can be implemented by adapting a digital FIR Gaussian transmit filter such that its filter characteristic reflects the intended modulation data amplification as well as enables Gaussian Frequency Shift Keyed modulation. With this implementation, no additional componentry beyond the PLL system is needed to implement the digital modulation data processing provided by the invention.