The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2003

Filed:

Sep. 28, 2001
Applicant:
Inventors:

Prateek Dujari, Portland, OR (US);

Franklin Monzon, Temple City, CA (US);

Pooya Tadayon, Hillsboro, OR (US);

Assignee:

Intel Corporation, Hillsboro, OR (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/3495 ;
U.S. Cl.
CPC ...
H01L 2/3495 ;
Abstract

A device and method for increasing input/output from a die by making electrically conductive microvias connecting the integrated circuit with a backside of the die. The backside electrically conductive microvias connect an integrated circuit in the die to pads on the backside of the die. A superstrate is situated on top of the die and connects to the microvias using controlled collapse chip connections (C4) with a thermal interface material (TIM) surrounding the electrical connections. A superstrate lead system electrically connects the backside pads to wirebonds that connect with either the substrate or directly to the motherboard. Heat dissipates from the die via the TIM to the superstrate to a heat sink situated on top of the superstate.


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