Self-aligned method for fabricating a capacitor under bit-line (cub) dynamic random access memory (dram) cell structure

Abstract

Within a method for fabricating a dynamic random access memory (DRAM) cell structure there is first anisotropically sequentially etched a blanket hard mask layer and a blanket capacitor plate layer which both cover a bit-line source/drain region within the dynamic random access memory (DRAM) cell structure to thus provide a patterned hard mask layer and a patterned capacitor plate layer which define a via. The patterned capacitor plate layer is then isotropically etched and recessed beneath the patterned hard mask layer, while forming from the via an enlarged via. There is then formed over the patterned hard mask layer, and completely filling the enlarged via, an inter-metal dielectric (IMD) layer. There is then anisotropically etched the blanket inter-metal dielectric (IMD) layer to form a patterned inter-metal dielectric (IMD) layer which in part defines a biaxially extended via at the location of the via, wherein portions of the patterned inter-metal dielectric (IMD) layer which define the biaxially extended via passivate sidewall portions of the isotropically etched patterned capacitor plate layer.