The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6625880 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 30, 2003

Filed:

Mar. 02, 2001
Applicant:
Inventors:

Yoshie Nabemoto, Ishikawa, JP;

Nobuo Komatsu, Tokyo, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 3/36 ;
U.S. Cl.
CPC ...
H05K 3/36 ;
Abstract

A multi-layer printed wiring board is manufactured by forming a wiring pattern and a component mounting portion on a first substrate. An insulating spacer, formed with a first opening, is stacked over the first substrate with the first opening in registration with the component mounting portion. A second substrate is stacked over the spacer and the resulting assembly is bonded together. A second opening, continuing to the first opening, is formed in the second substrate, exposing the component mounting portion to the outside. An LSI is mounted on the component mounting portion, the first and second openings are filled with a synthetic resin mass, and then a third substrate is stacked over the second substrate to enclose the openings.


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Nabemoto, Yoshie. (2003). Method for producing printed wiring board (U.S. Patent No. 6625880). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6625880

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