The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2003

Filed:

Feb. 28, 2000
Applicant:
Inventors:

Edoardo Charbon, Berkeley, CA (US);

Ilhami H. Torunoglu, San Jose, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

A system and method for protecting circuit designs from unauthorized use involves techniques for watermarking by embedding a hidden, recognizable input/output signature or code into the circuit design. An internal sequential function, such as a finite state machine, within the circuit design is used to generate a predictable output sequence when a known input sequence is applied. The free input configurations in the internal sequential function of the circuit design are identified and modified to generate the desired output sequence when the known input sequence is applied. A path among the free input configurations is selected, with output values in the desired output sequence being assigned the various state transitions. If there are not enough free input configurations to meet specified watermarking robustness criteria, then additional free input configurations may be added by, for example, adding one or more inputs, outputs or states to the finite state machine. Various techniques for arriving at an optimal path so as to minimize overhead caused by the addition of the watermark are also disclosed.


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