The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2003
Filed:
Nov. 20, 2001
Hirohito Higashi, Kawasaki, JP;
Hideki Ishida, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A bias current IB additionally provided to a current-controlled circuit in a PLL circuit is the sum of bias currents IB and IB which are generated by a bias adjustment circuit ( and ) and a bias current generating circuit ( and ), respectively. The bias adjustment circuit adjusts the bias current IB in response to an adjustment start signal ADJ such that a control voltage VC converges to a reference voltage VREF, and ceases the adjustment when the convergence has been achieved. The reference voltage VREF is determined to be a value at an almost middle point in a range of the variable VC in the PLL circuit. The bias current generating circuit has a circuit generating a bias voltage VT and a circuit converting the VT into a current IB wherein the temperature characteristic of the bias voltage VT is reverse to that of the control voltage VC under the condition that the frequency of an oscillation signal OCLK is fixed.