The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2003

Filed:

Aug. 20, 2001
Applicant:
Inventors:

Yuan-Li Tsai, Taipei, TW;

Marcus Yang, Chang-Hua, TW;

Ralph Chen, Taichung, TW;

Heng-Chun Kao, Taipei, TW;

Ching-Chun Hwang, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/1311 ;
U.S. Cl.
CPC ...
H01L 2/1311 ;
Abstract

The method for forming high voltage device combined with a mixed mode process use an un-doped polysilicon layer instead of the conventional polysilicon layer. In the high resistance area, the ion implant is not used until the source region and the drain region are formed. A resistor is formed by etching oxide-nitride-oxide layer and performing ion implant process by using BF radical to the un-doped polysilicon layer to control the resistance. Then multitudes of contact are formed, wherein the high dosage of BF implant would reduce resistance between contacts and resistor.


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Tsai, Yuan-Li. (2003). Method for forming high resistance resistor with integrated high voltage device process (U.S. Patent No. 6624079). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6624079

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