The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2003
Filed:
Sep. 28, 2001
Prashant Saxena, Portland, OR (US);
Satyanarayan Gupta, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Described herein are two techniques referred to as “Adaptive Power Routing” and “Shield Sharing To Reduce Shield Count,” that allow power routing and signal routing to be integrated in a manner that provides more efficient and compact layout of design blocks as compared to traditional techniques. Adaptive power routing refers to completion of power routing to be postponed to the signal routing phase, at which time signal shielding requirements are also used to complete the power routing along with predefined power delivery constraints. Shield sharing optimization refers to the more efficient use of previously routed power lines and to the insertion of a reduced number of additional power lines so as to satisfy both shielding requirements and power supply requirements in a gridless environment. These two techniques allow routing in highly congested regions containing performance-critical and/or noise-sensitive signals to be manufactured using less die area than would be required with traditional routing methodologies and algorithms.